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Dataflow compiler for QNN inference on FPGAs

Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput

Icarus Verilog submodule of CIRCA project

Yosys submodule of CIRCA project

CIRCA is a framework for the automatic generation of approximate circuits, differentiating from existing frameworks by its flexible and modular design.

PaderBench repository contains the source code for the benchmarks included in the PaderBench.